Sram device

ABSTRACT

An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation under 37 C.F.R. §1.53(b) ofprior application Ser. No. 12/531,780, filed Sep. 17, 2009, by ShinichiOuchi et al. entitled SRAM DEVICE, which is a U.S.C. §371 National Phaseconversion of PCT/JP2008/054720, filed Mar. 14, 2008, which claimspriority of Japanese Application No. 2007-072903, filed Mar. 20, 2007,the entire contents of which are specifically incorporated by reference.The PCT International Application was published in the Japaneselanguage.

TECHNICAL FIELD

The present invention relates to a static random access memory (SRAM)device.

BACKGROUND ART

Today, in conventional SRAM devices, 6-transistor CMOS SRAM cells areconfigured using planar MOS field effect transistors.

However, miniaturization of the device dimensions, which is performedwith the aim of performance improvement such as integration density andoperation speed, increases variation in the characteristics of thedevice. The variation obviously affects the operation stability of theSRAM. That is, the performances of the respective devices deviaterandomly from the design target, so that mismatch occurs andbistability, which is indispensable for memory retention, is degraded.The variation in the device characteristics may eventually lead tomalfunction, so that the yield will be lowered in the production processand reliability of the information systems will be lowered.

As an index for evaluating bistability, noise margin can be employed.The noise margin is defined as the maximum voltage of the noiseamplitude which is allowed to be superposed on memory nodes. The noisemargin for a read operation, a read margin, is the most difficult toensure sufficiently among read, write and hold operations. Theabove-mentioned mismatch between the devices reduces the read margin.Therefore, when the SRAM device is designed, the noise margin isdesigned in advance so as to be large, so that it is possible to have alarge margin even when there are variations in the device'scharacteristics in the production process.

The read margin cannot be increased without limit by device design, butit is inextricably linked with another index called a write margin. Thewrite margin is defined as the maximum voltage amplitude which isallowed to be superposed on memory nodes when a write operation isperformed, or the maximum voltage amplitude which is allowed to besuperposed on word lines. When a circuit is designed such that the readmargin increases, the write margin decreases.

In a conventional 6-transistor SRAM device, there are a few methods toenhance both the read and write margins. This was because thetransistor's characteristics are fixed and it was difficult to changethe transistor's characteristics according to the read or writeoperations.

For example, in Patent Document 1, there is disclosed an SRAM cell whichuses double gate field effect transistors. The variation can be reducedto more than that of the known planar CMOS. Still, there was a problemwith the performance variation of the double gate field effecttransistors, and no method has been provided which increases both theread margin and the write margin.

In addition, in Patent Document 2, there is disclosed an SRAM devicewhich uses four-terminal double gate field effect transistors of whichtwo gates of the double gate field effect transistor are separated fromeach other. However, the SRAM device is configured to reduce the leakagecurrent. This circuit is too complicated as a circuit for increasingboth the read and the write margins at the same time. In addition, inPatent Document 2, there is no disclosure of the operation method or theperipheral devices for increasing both the read and the write margins.

Patent Document 1: Specification of US Patent Application Laid-OpenPublication No. 2006-068531

Patent Document 2: JP-A-2005-260607

DISCLOSURE OF INVENTION Problem to be Solved by the Invention

The present invention has been made to address the above-mentionedproblems, and an object is to provide an SRAM device which can increaseboth the read and write margins.

Means for Solving the Problems

The above-mentioned problems will be solved by the following means.

(1) An SRAM device using a four-terminal double gate field effecttransistor as a selection transistor, wherein the four-terminal doublegate field effect transistor comprises a gate which drives thetransistor and a gate which controls a threshold voltage, which areelectrically separated from each other, on both surfaces of a standingsemiconductor thin plate, and wherein a voltage used to reduce athreshold voltage is input to the gate which controls the thresholdvoltage of the selection transistor during a writing operation thanduring a reading operation.

(2) The SRAM device according to (1), wherein the gate which controlsthe threshold voltage of the selection transistor is connected to wiresarranged in a column direction parallel with a bit line.

(3) The SRAM device according to (1) or (2), further comprising, on eachcolumn, a circuit which calculates the logical product of a write enablesignal and a column selection signal which is output from a columndecoder, and generates a bias voltage according to the result.

(4) The SRAM device according to any one of (1) to (3), wherein a signalpotential of a word line is adjusted so as to reduce current leakagewhich flows through a bit line in a cell belonging to a row withoutbeing selected.

(5) The SRAM device according to (4), further comprising, on each row, acircuit which determines the signal potential suitable to an operationof a corresponding row on the basis of a row selection signal of a rowdecoder, and outputs the signal potential to a word line.

Effect of the Invention

According to this invention, the SRAM device which can increase both theread and write margins can be obtained. That is, according to theinvention, unlike the SRAM device according to the related art, theconductance of a selection transistor can be increased in a SRAM cellduring a writing operation, and decreased in the SRAM cell during areading operation. As a result, it is possible to increase both the readand write margins at the same time. In addition, according to theinvention as described in claim 4, it is possible to prevent an increasein current leakage in the selection transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a figure schematically illustrating a configuration of afour-terminal double gate field effect transistor.

FIG. 2 is a symbol illustrating a four-terminal double gate field effecttransistor in a circuit diagram.

FIG. 3 is a circuit diagram of an SRAM cell which comprises afour-terminal double gate field effect transistor as a selectiontransistor.

FIG. 4 is a circuit diagram of an SRAM device, in which the SRAM cellshown in FIG. 3 is applied, according to a first embodiment.

FIG. 5 is a circuit diagram specifically illustrating a level shifter401 which is applied in the SRAM device shown in FIG. 4.

FIG. 6 is a timing chart when the SRAM shown in FIG. 4 operates.

FIG. 7 is a circuit diagram of an SRAM device, in which the SRAM cellshown in FIG. 3 is applied, according to a second embodiment.

FIG. 8 is a circuit diagram specifically illustrating an inverter 701which is applied in the SRAM device shown in FIG. 7 and supplies a biasvoltage which controls a threshold voltage instead of a level shifter401.

FIG. 9 is a timing chart when the SRAM shown in FIG. 7 operates.

FIG. 10 is a figure illustrating a layout of an SRAM cell which isimplemented on a semiconductor substrate.

FIG. 11 is a circuit diagram of an SRAM cell which comprises afour-terminal double gate p-channel field effect transistor as aselection transistor.

FIG. 12 is a circuit diagram of an SRAM device, in which the SRAM shownin FIG. 11 is applied, according to a fifth embodiment.

FIG. 13 is a circuit diagram specifically illustrating a level shifter1201 which is applied in the SRAM shown in FIG. 12.

FIG. 14 is a timing chart when the SRAM shown in FIG. 12 operates.

FIG. 15 is a figure illustrating a layout of an SRAM cell which isimplemented on a semiconductor substrate.

REFERENCE SYMBOLS

100: SILICON ON INSULATOR (SOI) LAYER OF AN SOI WAFER WHICH IS FORMEDINTO A STANDING SEMICONDUCTOR THIN PLATE

200: n-CHANNEL FIELD EFFECT TRANSISTOR

205: p-CHANNEL FIELD EFFECT TRANSISTOR

300: SRAM CELL

401: LEVEL SHIFTER

402: CIRCUIT BLOCK COMPRISING ROW DECODERS, AND LATCHES OR REGISTERS

403: CIRCUIT BLOCK COMPRISING COLUMN DECODERS, AND LATCHES OR REGISTERS

701: CMOS INVERTER WHICH SUPPLIES BIAS VOLTAGE WHICH CONTROLS THRESHOLDVOLTAGE TO AN SRAM CELL INSTEAD OF 401

1100: SRAM CELL WHICH USES FOUR-TERMINAL DOUBLE GATE p-CHANNEL FIELDEFFECT TRANSISTOR AS A SELECTION TRANSISTOR

1201: LEVEL SHIFTER FOR DRIVING 1100

WL: WORD LINE AND SIGNAL THEREOF

BL, BL˜: BIT LINE

V_(G2): BIAS VOLTAGE SUPPLYING LINE WHICH CONTROLS THRESHOLD VOLTAGE ANDSIGNAL THEREOF

V_(G2,0), V_(G2,1): LOW LEVEL POTENTIAL AND HIGH LEVEL POTENTIAL OF BIASVOLTAGE SIGNAL WHICH CONTROLS THRESHOLD VOLTAGE

MC: MEMORY CELL 300 OR 1100

PC: PRE-CHARGE CIRCUIT

PCE: OUTPUT SIGNAL OF PRE-CHARGE CIRCUIT

SEL: SELECTOR CIRCUIT

Read/Write: READING-WRITING CIRCUIT BLOCK

WE, WE˜: WRITE ENABLE SIGNAL AND NEGATIVE LOGICAL SIGNAL THEREOF

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a figure schematically illustrating a device structure of afour-terminal double gate field effect transistor which constitutes anSRAM cell. Reference numeral 100 in FIG. 1 represents a Silicon OnInsulator (SOI) layer of an SOI wafer which is formed into a standingsemiconductor thin plate. Reference numerals 101 and 102 represent asource electrode and a drain electrode which are highly doped with animpurity. Reference numerals 103 and 104 represent a first gateelectrode and a gate insulating film. Reference numerals 105 and 106represent a second gate electrode and a gate oxide film. Referencenumeral 107 is a buried oxied (BOX) layer. Reference numeral 108represents a semiconductor substrate layer. The first gate electrode andthe second gate electrode are electrically separated and placed onopposite surfaces of a fine semiconductor thin plate which is standing.

Further, it is known that a device formed from the bulk wafer, withoutan SOI structure, realizes the same function as that of the device shownin FIG. 1, where 104 and 108 are formed from the identical silicon layerand 107 is deposited. Therefore, the invention can be similarly appliedon a device which is created from such a bulk wafer.

When the first gate electrode 103 of the four-terminal double gate fieldeffect transistor is used as a signal input gate and the second gateelectrode 105 is used as a bias voltage input gate, a threshold voltageof the transistor as viewed from the signal input gate can be changed byan input voltage of the bias voltage input gate. As a result, a similareffect to the substrate bias effect in a bulk planar MOS can beattained. In this case, unlike the case of the bulk planar MOS, when anintegrated circuit is configured with the devices, the thresholdvoltages of the respective devices can be controlled independently.

FIG. 2 shows symbols of the four-terminal double gate field effecttransistor. A device 200 represents an n-channel field effecttransistor. A device 205 represents a p-channel field effect transistor.The terminals of the n-channel field effect transistor 200 consist of asource terminal 201, a drain terminal 202, a first gate terminal 203,and a second gate terminal 204. The terminals of the p-channel fieldeffect transistor 205 consist of a source terminal 206, a drain terminal207, a first gate terminal 208, and a second gate terminal 209.

First Embodiment

As described above, the four-terminal double gate field effecttransistor is used as the selection transistor. Each transistorconstituting flip-flops is configured with a usual double gate fieldeffect transistor of which two gates are connected. As a result, a6-transistor SRAM cell is configured as shown in FIG. 3.

The terminals of the threshold voltage control gate of the four-terminaldouble gate field effect transistor, are connected to the wires parallelto bit lines BL and BL˜. Here, each MN31 and MN32 is different from thefour-terminal double gate field effect transistor, and is a usualn-channel double gate field effect transistor of which two gates areconnected to each other. MP31 and MP32 are the general p-channel doublegate field effect transistors. In addition, the selection transistorsMN33 and MN34 are the four-terminal double gate n-channel field effecttransistors.

The SRAM cell shown in FIG. 3 is applied in the SRAM device shown inFIG. 4 and signal waveforms shown in FIG. 6 are input. With theconfiguration, a basic function regarding the optimization of the readand write margins, which is disclosed in the invention, is realized.Here, reference numeral 401 represents a level shifter, and an innercircuit thereof is shown in FIG. 5. In FIG. 5, MN51 and MN52 are then-channel field effect transistors, and MP51 and MP52 are the p-channelfield effect transistors.

In addition, a driver (buffer-amp) may be inserted into the followingstage of the level shifter 401 in order to drive interconnectionaccording to a required speed.

Here, reference numerals 402 and 403 respectively represent a circuitblock comprising row decoders, and latches or registers and a circuitblock comprising column decoders, and latches or registers.

Further, either the usual double gate field effect transistors or theconventional bulk planar MOS field effect transistors are applicable tothe field effect transistors MN51, MN52, MP51, MP52, and thoseconstituting 402, and 403.

The SRAM device shown in FIG. 4 operates as described below.

(1) A pre-charge circuit PC inputs a signal PCE to the bit lines BL toBL˜ on the basis of a clock signal CLK, and performs pre-charging.

(2) Row addresses and column addresses are respectively decoded by 402and 403. For example, when an address (i, k) is specified from “M×N”addresses in total, X[i] and a column selection signal Y[k] are raisedafter the pre-charging operation as shown in FIG. 6.

(3) X[i], and Y[k]·WE which is the logical product of the write enablesignal WE and Y[k] are level shifted by the level shifter 401, and thesignals WL[i] and V_(G2)[k] are generated. In the first embodiment, asone example, the signals X and Y·WE ranging from 0 V to 1 V areconverted to the signals ranging from −1 V to 1 V. In an example shownin FIG. 5, the cell, of which address is (i, k), is selected for a readoperation, namely WE=0. At this time, V_(G2)[k] is −1 V. Since thethreshold voltage of the MN33 and MN34 is increased by V_(G2) of −1 Vand the conductance thereof is lowered, the read margin is increased.

(4) On the contrary, for example, when the WE turns to 1 and a writeoperation is executed on the cell (j, l), V_(G2)[l] turns to 1 V asshown in FIG. 6. Therefore, since the threshold voltage of the MN33 andMN34 is reduced and the conductance thereof is higher, the write marginis increased.

Here, since the V_(G2) is set to be lower when the reading is performed,all the selection transistors MN33 and MN34 of the unselected cell cometo be in a sufficiently strong off state. However, since the V_(G2)comes to be 1 V when the writing is performed, both transistors come tobe in a state of V_(G2)=1 V at the same time even on unselected rows,the both transistors are almost in the on-state, so that there may be arisk of memory destruction. In order to avoid this, a potential (whichas an example corresponds to −1 V in this embodiment) lower than aground potential of the cell is input to the WL on the unselected rowswithout being selected, and the strong off state is maintained.

Further, when a power supply voltage is appropriately selected accordingto the configuration of the device, a low level potential of the V_(G2)or WL is accordingly also appropriately selected.

Second Embodiment

By selecting the capacitance of the gate insulating film and workfunction of the second gates 204 to 209 of the four-terminal double gatefield effect transistor, the signal level, that is, the potential usedin the V_(G2) and WL can be changed (refer to JP-A-2005-167163 andJP-A-2005-174960). Using this method appropriately, the invention can beapplied even though either or both the V_(G2) and WL is changed in arange of V_(SS) [=0]≦V_(G2)≦V_(DD), V_(SS) [=0]≦V_(WL)≦V_(DD). Here, theconfiguration shown in FIG. 4 can be simplified as shown in FIG. 7. Thatis, the level shifter 401 is omitted from each row, and a CMOS inverter701 shown in FIG. 8 is inserted instead of the level shifter 401 in eachcolumn, so that the same effect as that of the first embodiment can beattained. In FIG. 8, the MN71 is the n-channel field effect transistor,and the MP71 is the p-channel field effect transistor. Either the usualdouble gate field effect transistors or the conventional bulk planar MOSfield effect transistors are applicable to these MN71 and MP 71. As aresult, the timing chart shown in FIG. 6 is the same as that shown inFIG. 9.

In this case, the V_(G2) during the writing can be increased in a rangeas long as the MN33 and MN34 do not turn to the on-state when they arenot selected (when V_(WL)=0 V). That is, the highest potential allowedfor the V_(G2) corresponds to a threshold voltage V_(TH0) of the secondgate when the V_(WL)=0 V.

Third Embodiment

In this embodiment, a layout when a memory cell 300 is implemented on asemiconductor substrate in practice is disclosed. FIG. 10 is a figureillustrating the layout of the SRAM cell which is implemented on thesemiconductor substrate. By configuring the four-terminal double gatefield effect transistor so as to be symmetrical about a point, thememory cell shown in FIG. 3 is implemented on the semiconductorsubstrate. Further, in FIG. 10, wires in second and third metal layersare respectively denoted by a solid line and a dotted line so as to besimply displayed. In addition, the symbol x shown in FIG. 10 indicatesthe positions of contacts or via holes.

Fourth Embodiment

There has been known that the second gate oxide film 106 of thefour-terminal double gate field effect transistor is formed to bethicker than the first gate oxide film 105, so that the ON-OFFcharacteristics of the transistor can be improved. (M. Masahara et al.“Demonstration of asymmetric gate-oxide thickness four-terminal Fin FETshaving flexible threshold voltage and good subthreshold slope”, IEEEElectron Device Letters, vol. 28, no. 3, pp. 217-219, March 2007.)

The knowledge can be also applied to the MN33 and MN34 according to theinvention.

Fifth Embodiment

In the first to fourth embodiments, the MN33 and the MN34 are configuredwith the n-channel devices. However, these are configured with p-channeldevices MP33 and MP34, so that the system composition can be simplified.The examples of the composition are shown in FIGS. 11 to 15. In FIGS. 11to 15, the same components as those shown in FIGS. 3 to 10 are denotedby the same reference numerals. Here, V_(G2,0)′ and V_(02,1)′respectively correspond to V_(G2,0) and V_(G2,1), and can berespectively realized by a positive voltages greater than 0 V, forexample 2 and 0 V respectively. In an integrated circuit, a corecontaining calculation or storage devices is usually designed to operateat a low voltage such as 0.0 to 1.0 V, and an interface with an externalcircuit operates at a voltage higher than that of the core such as 0.0to 3.3 V. In this embodiment, it is possible to use the voltage, whichis used in such a peripheral circuit, directly or by reducing itsvoltage with a regulator. Therefore, a system can be configured withoutusing negative voltage. The level shifter is configured such as 1201. Inthis case, the operation speed may be adjusted by inserting a driver(buffer-amp) into the following stage of 1201 in order to drive theinterconnection.

The layout can be realized in a structure shown in FIG. 15 because thisis implemented by using semiconductor thin plate structures, unlike thebulk planar MOS. Further, in FIG. 15, wires in second and third metallayers are respectively denoted by a solid line and a dotted line so asto be simply displayed. In addition, the symbol x shown in FIG. 15indicates the positions of contacts or via holes.

What is claimed is:
 1. An SRAM device using a four-terminal double gatefield effect transistor as a selection transistor, wherein thefour-terminal double gate field effect transistor comprises a gate whichdrives the transistor and a gate which controls a threshold voltage,which are electrically separated from each other, on both surfaces of astanding semiconductor thin plate, and wherein a voltage used to reducea threshold voltage is input to the gate which controls the thresholdvoltage of the selection transistor during a writing operation thanduring a reading operation, wherein the gate which controls thethreshold voltage of the selection transistor is connected to wiresarranged in a column direction parallel with a bit line; and wherein theSRAM cell comprises a first half cell and a second half cell, each halfcell comprising an inverter and a selection transistor, the invertercomprising a first transistor having a first conductivity channel and asecond transistor having a second conductivity channel, the inverterworking as a component of a flip-flop together with an inverter in thecounter-part half cell, the selection transistor in the half cellcomprising the four-terminal double gate field effect transistor, asource, a drain, and a gate of the first transistor and a source, adrain, and a gate of the second transistor in the inverter beingconfigured side-by-side, respectively, a contact to the gate of thefirst transistor and a contact to the gate of the second transistorbeing collectively implemented by a single contact being configuredbetween the first and the second transistors, each four-terminal doublegate field effect transistor comprising a standing semiconductor thinplate being aligned on the straight line running on the source and thedrain of the first transistor in each inverter in each half cell, thedrain of the first transistor in each inverter being connected to thestanding semiconductor thin plate of the four-terminal double gate fieldeffect transistor in each half cell via a single contact, the first gateof the four-terminal double gate field effect transistor which drivesits selection operation being formed on the surface of the standingsemiconductor thin plate facing outside the cell, the second gate of thefour-terminal double gate field effect transistor which adjusts itsthreshold voltage being formed on the surface of the standingsemiconductor thin plate facing on the side where the gate contact forthe input of the inverter is configured in reference to the line runningon the standing semiconductor thin plane, the wire which distributes thebias voltage which adjusts threshold voltage being implemented inparallel with a bit line, the first half cell and the second half cellbeing configured to be symmetrical about a point, and the contact to thefirst gate of the four-terminal double gate field effect transistorbeing implemented on the boundary of a neighbor memory cell.
 2. The SRAMdevice according to claim 1, wherein a potential lower than a groundpotential of a cell is input to a word line when the word line is notselected.
 3. The SRAM device according to claim 1, wherein the SRAM cellcomprises a first half cell and a second half cell, each half cellcomprising an inverter and a selection transistor, the invertercomprising a first transistor having a first conductivity channel and asecond transistor having a second conductivity channel, the inverterworking as a component of a flip-flop together with an inverter in thecounter-part half cell, the selection transistor in the half cellcomprising the four-terminal double gate field effect transistor, asource, a drain, and a gate of the first transistor and a source, adrain, and a gate of the second transistor in the inverter beingconfigured side-by-side, respectively, a contact to the gate of thefirst transistor and a contact to the gate of the second transistorbeing collectively implemented by a single contact being configuredbetween the first and the second transistors, each four-terminal doublegate field effect transistor comprising a standing semiconductor thinplate being aligned on the straight line running on the source and thedrain of the first transistor in each inverter in each half cell, thedrain of the first transistor in each inverter being connected to thestanding semiconductor thin plate of the four-terminal double gate fieldeffect transistor in each half cell via a single contact, the first gateof the four-terminal double gate field effect transistor which drivesits selection operation being formed on the surface of the standingsemiconductor thin plate facing outside the cell, the second gate of thefour-terminal double gate field effect transistor which adjusts itsthreshold voltage being formed on the surface of the standingsemiconductor thin plate facing on the side where the gate contact forthe input of the inverter is configured in reference to the line runningon the standing semiconductor thin plane, the wire which distributes thebias voltage which adjusts threshold voltage being implemented inparallel with a bit line, the first half cell and the second half cellbeing configured to be symmetrical about a point, the contact to thefirst gate of the four-terminal double gate field effect transistorbeing implemented on the boundary of a neighbor memory cell, and whereina potential lower than a ground potential of a cell is input to a wordline when the word line is not selected.
 4. The SRAM device according toclaim 1, further comprising, on each column, a circuit which calculatesthe logical product of a write enable signal and a column selectionsignal which is output from a column decoder, and generates a biasvoltage according to the result.
 5. The SRAM device according to claim1, wherein a signal potential of a word line is adjusted so as to reducea current leakage which flows through a bit line in a cell belonging toa row without being selected.
 6. The SRAM device according to claim 5,further comprising, on each row, a circuit which determines the signalpotential suitable to an operation of a corresponding row on the basisof a row selection signal of a row decoder, and outputs the signalpotential to a word line.
 7. The SRAM device according to claim 2,further comprising, on each column, a circuit which calculates thelogical product of a write enable signal and a column selection signalwhich is output from a column decoder, and generates a bias voltageaccording to the result.
 8. The SRAM device according to claim 2,wherein a signal potential of a word line is adjusted so as to reduce acurrent leakage which flows through a bit line in a cell belonging to arow without being selected.
 9. The SRAM device according to claim 8,further comprising, on each row, a circuit which determines the signalpotential suitable to an operation of a corresponding row on the basisof a row selection signal of a row decoder, and outputs the signalpotential to a word line.
 10. An SRAM device using a four-terminaldouble gate field effect transistor as a selection transistor, whereinthe four-terminal double gate field effect transistor comprises a gatewhich drives the transistor and a gate which controls a thresholdvoltage, which are electrically separated from each other, on bothsurfaces of a standing semiconductor thin plate, and wherein a voltageused to reduce a threshold voltage is input to the gate which controlsthe threshold voltage of the selection transistor during a writingoperation than during a reading operation, wherein the gate whichcontrols the threshold voltage of the selection transistor is connectedto wires arranged in a column direction parallel with a bit line; andwherein the SRAM cell comprises a first half cell and a second halfcell, each half cell comprising an inverter and a selection transistor,the inverter comprising a first transistor having a first conductivitychannel and a second transistor having a second conductivity channel,the inverter working as a component of a flip-flop together with aninverter in the counter-part half cell, the selection transistor in thehalf cell comprising the four-terminal double gate field effecttransistor, a source, a drain, and a gate of the first transistor and asource, a drain, and a gate of the second transistor in the inverterbeing configured side-by-side, respectively, a contact to the gate ofthe first transistor and a contact to the gate of the second transistorbeing collectively implemented by a single contact being configuredbetween the first and the second transistors, each four-terminal doublegate field effect transistor comprising a standing semiconductor thinplate being aligned on the straight line running on the source and thedrain of the first transistor in each inverter in each half cell, thedrain of the first transistor in each inverter being connected to thestanding semiconductor thin plate of the four-terminal double gate fieldeffect transistor in each half cell via a single contact, the first gateof the four-terminal double gate field effect transistor which drivesits selection operation being formed on the surface of the standingsemiconductor thin plate facing outside the cell, the second gate of thefour-terminal double gate field effect transistor which adjusts itsthreshold voltage being formed on the surface of the standingsemiconductor thin plate facing on the side where the gate contact forthe input of the inverter is configured in reference to the line runningon the standing semiconductor thin plane, the wire which distributes thebias voltage which adjusts threshold voltage being implemented inparallel with a bit line, the first half cell and the second half cellbeing configured to be symmetrical about a point, the contact to thefirst gate of the four-terminal double gate field effect transistorbeing implemented on the boundary of a neighbor memory cell, and whereina potential lower than a ground potential of a cell is input to a wordline when the word line is not selected.
 11. The SRAM device accordingto claim 10, further comprising, on each column, a circuit whichcalculates the logical product of a write enable signal and a columnselection signal which is output from a column decoder, and generates abias voltage according to the result.
 12. The SRAM device according toclaim 10, wherein a signal potential of a word line is adjusted so as toreduce a current leakage which flows through a bit line in a cellbelonging to a row without being selected.
 13. The SRAM device accordingto claim 12, further comprising, on each row, a circuit which determinesthe signal potential suitable to an operation of a corresponding row onthe basis of a row selection signal of a row decoder, and outputs thesignal potential to a word line.